- Responsible for leading and building a strong physical design team in China 
- Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure and able to create the GDSII for tape out - The candidate will have the opportunity to work on many varieties of challenging design projects. 
- Ability to handle large sized design implementation tasks alone 

Requirements:


 - Must have hands on physical design and verification experience in the past two years in large scale ASIC chip physical design, 28 nm experience is preferred
- BS degree with 8+ years of applicable experience, MS degree with 5+ years of applicable experience in electrical engineering, microelectronics.
- Experienced with ASIC design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues. Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM. Successful track records of taping out complex, 65/40/28 nm SOC chips.
- Successfully gone through several complete product development cycle as a backend leader 
- Self-motivated, able to work independently or as a team player, customer focus, accountability, effective communicator, able to coach and provide feedback and develop others 
- Excellent verbal and written communication skills in English and project management skills 
- not only technical excellent but also mature & able to communicate with customers
 - Self-initiative, quick learner, eager to learn new technologies 
- Good at multi-tasking and priority setting
- Innovative and sensitive in not only the technical delivery, but also the new business opportunity