Job Description:
1.This position is for a digital/ASIC design engineer to build next-generation analog/mixed-signal SoC chipsets.
2.Work closely with analog/mixed-signal designers to build robust system-on-chip that is reliable under PVT variation.
3.Handle many aspects of ASIC design flow including: architecture, RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
4.Participate in chip debug, validation, and marketing specifications.
 
Qualifications:
1.BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
2.Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication, integration), timing analysis, DFT, meta-stability, etc.
3.Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, and decimation.
4.Desired usage experience of mainsteam industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
5.Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
6.Experience in common protocols, such as bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
7.Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
8.Experience in mixed-signal SOC design is a plus.
9.Experience in perl/python/tcl scripts is a plus.