Job Description:              
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
 
Job Requirement:

1. MSEE with 6+ years or Bachelor with 8+ years of industrial experience in ASIC design
2. 5+ years or more years of experience in physical design of deep submicron digital ASIC chips
3. Hands on experience in large scale ASIC chip physical design
4. Knowledgeable in all aspects of deep submicron ASIC design flow
5. Successfully gone through several complete product development cycles
6. Demonstrate strong leadership and work well with cross-functional teams
7. Good listening, writing and speaking English
8. Good communication skills, strong interpersonal skills and the flexibility
9. Dedicated, hardworking and good team player
10. Familiar with Back-End (physical design) EDA tools
11. Familiar with Front-End EDA tools is a plus
12. Familiar with Unix/Linux environment and good at scripts