- 19.2萬-33.6萬/年
- 上海
- |
- 工作經(jīng)驗不限
- |
- 碩士
- |
- 全職
職位誘惑: 五險一金,福利好,老板nice,成長空間大
發(fā)布時間: 2019-12-10發(fā)布
職位描述
Job Requirements:
- Solid understanding of analog/mixed signal IC design, including feedback theory, device mismatch, signal noise, phase noise, jitter and jitter tolerance.
- Silicon experience on one or more areas in the following: Sigma delta ADC, SAR ADC, High speed DAC, power management, audio codec, and timing circuits such as PLL, clock-and-data recovery (CDR), TX and RX functions.
- Lab characterization and debug experience is desirable.
- Familiar with EDA tools such as Cadence Design Systems, matlab is a plus
- Verilog & verilogA coding and simulation is a significant plus.
- Must be a self-starter and team player.
Education Requirements:
M.S./PhD in EE.
職位發(fā)布者
ASR HR
VP
7天
簡歷處理用時
100%
滬公網(wǎng)安備31011502017136號