Sr. /MTS Engineer for Front-End integration
Responsibility:
• Integrate functional IPs into SoC per architectural requirement.
• Develop RTL code for macro blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
• Participate in making functional/technology based chip targets in timing, area, power. Develop timing constraint, power intent spec accordingly.
• Synthesis and deliver qualified netlist, cowork with PD to settle chip floorplan and achieve timing closure.

Requirement:
• Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences in ASIC Company. 
• Familiar with one or more ASIC flows (logic synthesis, STA, formality check, Design for Power ) and usage of related EDA tools.
• Familiar with script languages ((tcl, perl etc.) in unix/linux.
• Familiar with IO analog macro knowledge is a plus
• Good problem solving and communication skills
• Good written and spoken English.
• Good communication skills and be able to work both independently and in a team.