Education: MS/BS in EE/CS (MS preferred).
Experience; Minimum 2 years of experience with MSEE/CS or 4 years with BSEE/CS.
Requirements: 

¨        Familiar with FPGA design tools: Synplify, Vivado, ISE, Quartus
¨        Familiar with Xilinx/Altera FPGA architecture
¨        Familiar with FPGA development, especially FPGA logic design, FPGA RTL coding, FPGA constrain setup, verification, synthesis, par and timing closure
¨        One or more advantages of the followings are highly desirable: Hands-on experience in WIFI/Ethernet/PCIe/USB/SATA/SDIO/ARM CPU/DDR3/DDR4 emulation. Familiar with hardware schematics.
¨        Excellent teamwork, interpersonal and communication skills.
¨        Fluent in Chinese and English both verbal and written.
¨        Scripting/programming skill in C/C++, Tcl, Perl/Csh desired.
¨        Ability to work in stressful situations with tight schedules to meet.

Description of Function & Responsibility:

¨        Port the state of the art ASIC design to the advanced FPGA platform for emulation.
¨        Take ownership of FPGA image build flow, FPGA image building and FPGA design documentation.
¨        Interact with external IP teams/vendors to resolve all FPAG related technical implementation and integration issues.
¨        Work closely with other Design/DV/Validation/SW teams for bug/issue debug, support and chip bring-up