崗位職責(zé)：
1.  熟悉基于CMOS工藝的射頻和模擬IC版圖設(shè)計(jì)與校驗(yàn)
2.  后仿真參數(shù)提取
3.  負(fù)責(zé)版圖的標(biāo)準(zhǔn)單元設(shè)計(jì)，模塊設(shè)計(jì)，tape out等
4.  與設(shè)計(jì)工程師高效合作，完成設(shè)計(jì)性能指標(biāo)
任職要求：
1.   本科以上學(xué)歷，工科相關(guān)專業(yè)
2.   1年以上相關(guān)工作經(jīng)驗(yàn)
3.   熟練使用各種版圖設(shè)計(jì)工具
4.   熟悉基于CMOS的射頻和模擬集成電路的相關(guān)知識(shí)
5.   良好的口頭及書寫表達(dá)能力，跨團(tuán)隊(duì)合作能力
6.   良好的團(tuán)隊(duì)合作精神，優(yōu)秀的學(xué)習(xí)能力及積極獨(dú)立的主動(dòng)工作能力
Analog and RF IC Layout engineer
Position Overview:
1.   Familiar with CMOS analog or RF IC layout, verification of the layout (DRC/ERC/LVS),
2.   RC extraction for post simulation
3.   Responsible for all levels of analog or RF layout from top level floor plan, block level design, top level integration and tape out.
4.   Communicate and get directions from analog design Engineer to ensure high quality.
Requirements:
1.   Above Bachelor degree in Microelectronics or equivalent areas
2.   Must have 1+ year Analog or RF IC layout design experience. Full chip integration and tape out experience is a plus.
3.   Familiar with Cadence virtuoso and Calibre verification tools. Experience with Dracula, Hercules, Assura etc. is a plus.
4.   Must have a good Understanding of basic CMOS design, process and device matching.
5.   A team player with good oral and written communication skills, ability to work in cross-functional team.
6.   Can work highly independently, actively. Good learning ability,communication and teamwork skills.