- 12萬-24萬/年
- 上海
- |
- 1-3年
- |
- 本科
- |
- 全職
職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,老板nice,股票期權(quán),技術(shù)領(lǐng)先,成長空間大,十八薪
發(fā)布時(shí)間: 2019-07-05發(fā)布
職位描述
Responsibilities：
Handle all aspects of chip backend design, including floor planning, place and routing, CTS, timing convergence iterations/optimization, DFT and final DRC/LVS.
Qualifications:
1. BSEE, MSEE or higher.
2. 2~4 years experience of large ASIC backend designs.
3. Experience with Synopsys and/or Cadence design tools.
4. Familiar with 45/40nm or lower CMOS process designs.
5. Having successful tape out experience will be a great plus.
6. Good communication skills, team spirit and be anxious to learn during daily work.
職位發(fā)布者
Photonic HR
7天
簡歷處理用時(shí)
100%
簡歷及時(shí)處理率
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光梓信息科技（上海）有限公司
領(lǐng)域: 通信網(wǎng)絡(luò)
規(guī)模: 0-50人
主頁: http://www.photonic-tech.com
工作地址:
浦東區(qū)亮秀路112號(hào)Y1樓710 （地鐵2號(hào)線金科路站）
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滬公網(wǎng)安備31011502017136號(hào)