Description:
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design
2. Generating, simulation and debugging the test patterns for ATE manufacture testing
3. Interface with back-end physical design team to complete timing closure for test related logic
4. Interface with operation team to debug production test-vectors for wafer test and final test
 
Qualification:
1. BS or MS, major in EE or related discipline
2. Strong experience in ASIC logic design and verification
3. 3+ years work experience in ASIC DFT design
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability
5. Good communication capability and teamwork spirit