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ASR

cellular RFIC design engineer

收藏職位
  • 我要分享
  • 18萬-26.4萬/年
  • 上海
  • |
  • 3年以上
  • |
  • 碩士
  • |
  • 全職

職位誘惑: 五險(xiǎn)一金,十五薪,老板nice

發(fā)布時(shí)間: 2019-12-10發(fā)布

職位描述


Job description:
 
            Become a member of our cellular communication team working on state of the art wireless solutions for LTE, WCDMA, GSM and other wireless standards. Designers have the opportunity to work on different parts of high performance transceiver including:
·          

  • Filters, TIAs and other analog blocks
  • Receiver frontend, including LNAs, mixers and LO chain
  • On chip PA, or pre-PA drivers
  • PLL building blocks including VCOs
 
  The designers participate on system architecture and implementation of the full transceiver including integration with digital back end. They will be engaged in package design, and chip evaluation.
 
Job Requirements:
 
  • Ph.D  with research emphasis in CMOS RF/analog design or  Master Degree with 3-4 years of experience in CMOS analog/RF circuit design
  • Demonstrate solid background in Analog and RF design, familiar with basic building blocks such as amplifiers, LNAs, VCOs, PLLs and other RF and analog blocks.
  • Possess a strong understanding of wireless systems and familiar with different RX/TX architectures.
  • Proficient with Cadence Spectre (RF), GoldenGate, virtuoso or similar simulation and layout tools
  • Experience with EM simulation tools such as HFSS and EMX

職位發(fā)布者

ASR HR

VP

7天

簡歷處理用時(shí)

100%

簡歷及時(shí)處理率

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