CPU驗證工程師（北京/蘇州）
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崗位職責：
1 開發(fā)處理器核、多核以及模塊級驗證環(huán)境
2 制定驗證計劃
3 開發(fā)/運行/調試測試用例以及功能覆蓋點
4 使用多種驗證工具、平臺，例如形式化驗證工具，Emulator
5 開發(fā)/維護仿真測試平臺基礎設施
 
所需技能：
1 計算機科學、計算機工程或電子工程等相關專業(yè)學位
2 有以下至少一項經驗
  - 計算機體系結構知識
  - 驗證環(huán)境開發(fā)，如UVM/OVM
  - 編寫測試用例，開發(fā)檢查器，覆蓋率分析，錯誤調試，錯誤原因分析
  - 形式化驗證
  - 指令集模擬器
  - 匯編語言編程，隨機指令序列生成器，系統(tǒng)底層軟件
3 熟悉以下至少一種編程語言：C/C++, Perl, Python, Ruby
4 良好的團隊合作精神，工作態(tài)度積極
 
CPU DV Engineer
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Responsibilities:
You will work in fast growing team and will participate in one or several of below tasks
1 Define/develop the verification environment for the core, core submodule, and full chip
2 Create verfication test plans
3 Develop/run/debug testcases and function coverage
4 Use a wide set of verification tools and platforms, including formal verification tool, emulator
5 Develop/maintain regression infrastruction for core DV
 
Qualifications:
1 M.S. or B.S. in Computer Science or Computer Engineering or Electrical Engineering
2 Experience in at least one of following areas:
  - Computer architecture knowledge
  - Verification environment development in Verilog, Specman, System Verilog UVM/OVM
  - Verification and debug experience including testcase writing/generation, checker
    development, coverage analysis, failure debug, root cause analysis
  - Formal verification
  - Instruction set simulator (ISS)
  - Assembly language programming, code generation, or other low-level software experience.
3 Programming experience in at least one language: C/C++, Perl, Python, Ruby, etc.
4 Strong communication and collaboration skills