- 30萬-42萬/年
- 上海
- |
- 3年以上
- |
- 本科
- |
- 全職
職位誘惑: 年終獎金,五險一金,交通補助,免費班車,技能培訓(xùn),成長空間大
發(fā)布時間: 2019-02-25發(fā)布
職位描述
Job Responsibilities:
-Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
-Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Job Requirements:
-Familiar with Verilog RTL design and has experience of large digital ASIC project.
-Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
-Familiar with unix/linux and scripts (tcl, perl etc.)
-Fluent English on talking, presentation and writing documents.
-Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
職位發(fā)布者
AMD
HR
簡歷處理用時
簡歷及時處理率
滬公網(wǎng)安備31011502017136號