ASIC Front-End Design Engineer

Responsibilities:
•     Develop RTL code for Block / IP or SoC top level
•     Working with project lead to define FEINT flow setting, including synthesis, equivalence check flow. Define frequency target, power strategy and etc.
•     Regular run FEINT flow, check quality, drive/co-work IP team on issue solving and QoR improvement.
•     Work very closely with physical design engineers to help on floorplan, timing closure, power design validation and etc.
•     Support ASIC bring-up.
 
Requirements:
•     Major in CS, EE or related, master or bachelor degree;
•     Knowledge of ASIC design (Digital circuit design, verilogHDL) is required;
•     Familiar with Linux working environment;
•     Familiar with EDA tools such as DC, Formality, PT, CDC/LEDA;
•     Strong knowledge of electronics fundamentals;
•     Strong analytical ability and problem solving skills with good team work spirit;