- 15萬-20萬/年
- 上海
- |
- 1-3年
- |
- 碩士
- |
- 全職
職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,福利好,老板nice,年底雙薪,年度旅游,成長空間大,技術(shù)領(lǐng)先,節(jié)日禮物,技能培訓(xùn)
發(fā)布時(shí)間: 2017-11-23發(fā)布
職位描述
Job Requirement
1. Highly efficient in Verilog RTL coding
2. Hands-on experience on ASIC/FPGA design, verification flows, methodologies, network protocol Validation
3. Good understanding of modulator/demodulator design related techniques is a plus
4. Hands-on experience on Ethernet MAC/Switch/Network processing accelerator or 802.11 MAC ASIC/FPGA implementation and verification is a plus
6. Good document skills in english
7. Expertise in verification methodology such as systemVerilog/UVM is a plus and highly desired
8. Bachelor's or master's degree in semiconductor, electronic engineering or relevant speciality
Job Responsibilities
1 .Perform full cycle of IP development responsibilities, from circuit simulation, FPGA verification to chip validation.
2. communication IP/IC design, implementation and verification
職位發(fā)布者
王津福
技術(shù)專家
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