Analog and Mixed-signal Design Engineer
- 12萬-24萬/年
- 天津
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- 應(yīng)屆生/在校生
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- 碩士
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- 全職
職位誘惑: 年終獎金,五險一金,福利好,老板nice,十五薪,年底雙薪,股票期權(quán),天天下午茶,年度旅游,技術(shù)領(lǐng)先,成長空間大,節(jié)日禮物
發(fā)布時間: 2021-09-14發(fā)布
職位描述
專業(yè)要求:
1.Analysis, design of high speed (1-6Gb/s) analog and mixed-signal integrated circuits for wireline applications, such as PLL, VCOs, high speed I/O, equalizer, SERDES, CDR, etc.
2.Custom design of high speed CMOS digital circuits.
3.Supervise layout of analog circuits and high-speed digital circuits.
4.Self-motivated and also able to work as member of a small team.
職位描述:
1.Experience and good understanding of analog and mixed-signal blocks, including some of the following areas: (a). PLL/DLL, regulators, VCOs, etc.(b). high speed (multi-Gbps) interfaces, wireline driver, receiver, equalizer, etc. (c). high speed SERDES, CDR.
2.Experience with design and layout tools such as Cadence Virtuoso, Cadence Spectre-RF, HSPICE, or other similar simulators and layout tools.
3.Good understanding of semiconductor devices and technology.
4.MS or PhD degree in analog and mixed-signal IC background.