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System Validation Engineer

收藏職位
  • 我要分享
  • 15萬(wàn)-25萬(wàn)/年
  • 成都
  • |
  • 應(yīng)屆生/在校生
  • |
  • 碩士
  • |
  • 全職

職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,福利好,成長(zhǎng)空間大

發(fā)布時(shí)間: 2021-02-19發(fā)布

職位描述

Job Description
As part of Marvell central system validation team, the SV engineer will mainly focus on following areas, but not limited to:
Validate different kinds of SoC, including function validation, performance validation and power consumption validation. And pre-silicon and post-silicon validation.
Develop system level software to cover complex use cases of different kinds of SoC.
Debug complex system level SoC issues which including software and hardware issues.
Cover the temperature, voltage and process validation of the SoC. 
Support different product lines as central platform on compliance test.
Support different kinds of SoC bring up and validate the bootrom.

Job requirements
Master’s degree in electrical engineering, computer engineering or related technical fields, 
Good knowledge of C, ARM architecture, embedded system software and device driver development.
Knowledge and experience of software and hardware debugging.
Knowledge of multi-core and multi-thread OS.
A high-level of self-motivation and a proactive approach to solving problems.
Good English communications skills.
Knowledge of PCIE, SATA, USB,NAND and WIFI is plus.
Experience of oscilloscope and logic analyzer is plus.

職位發(fā)布者

Nancy Wang

HR

7天

簡(jiǎn)歷處理用時(shí)

100%

簡(jiǎn)歷及時(shí)處理率

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