Job description:

• This position is for a DSP algorithms / digital design engineer to build next-generation analog/mixed-signal photonic SoC chipsets.
• Handle many aspects of ASIC design flow including: DSP simulations, system architecture design, RTL coding and Verification.
• Participate in chip debug, validation, and marketing specifications.

• MSEE with minimum 2-year experience or PhD with minimum 1-year experience of digital experience.
• Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication), timing analysis, DFT, meta-stability, etc.
• Fundamental understanding of digital signal processing, such as FIR/IIR filter structure, error correction, decimation, signal/noise tradeoffs, channel estimation, equalization, crosstalk, and BER evaluation.  
• Desired usage experience of mainsteam industry-standard EDA tools, such as Matlab, Simulink, VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
• Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
• Experience in mixed-signal SOC design is a plus.
• Experience in uvm/perl/python/tcl scripts is a plus.