Job description:

• This position is for a digital/ASIC design engineer to build next-generation photonic SoC chipsets.
• Handle many aspects of ASIC design flow including: RTL coding/Verification, Synthesis, DFT, STA and P&R (for backend designer).
• Participate in chip debug, validation, and marketing specifications.

• BSEE with minimum 3-year experience or MSEE with minimum 1-year experience of digital experience.
• Excellent knowledge of ASIC design, such as arithmetic structure (addition, multiplication), timing analysis, DFT, meta-stability, etc.
• Fundamental understanding of standard signal processing, such as FIR/IIR filter structure and decimation.
• Desired usage experience of mainstream industry-standard EDA tools, such as VCS/NC, Design Compiler, PrimeTime, Formality/ Conformal and Tetramax/DFT compiler.
• Experience in several vertical aspects of ASIC design (front-end and back-end) will be a great plus.
• Experience in bus design (I2C, AHB/APB/AXI), datapath design (Filter, correlation or Cordic) and logic control (PCS or MAS) is a plus.
• Experience in metrics-driven verification methodology (System-Verilog/UVM based) is a plus.
• Experience in mixed-signal SOC design is a plus.
• Experience in perl/python/tcl scripts is a plus.