- 40萬-80萬/年
- 青島
- |
- 工作經(jīng)驗不限
- |
- 碩士
- |
- 全職
職位誘惑: 年終獎金,五險一金,福利好,老板nice,股票期權(quán),技能培訓(xùn),技術(shù)領(lǐng)先,成長空間大
發(fā)布時間: 2022-11-03發(fā)布
職位描述
- MSEE degree
- 5+ years of digital system design experience in CMOS processes
- Working knowledge of Verilog RTL language and high level modeling tools (Simulink, Matlab ...)
- Working knowledge of digital design flow from architecture, RTL design, verification, synthesis and timing analysis
- Strong lab and silicone validation skills
- Familiarity with FIR filter design is a strong plus
職位發(fā)布者
劉瑞偉
HR
7天
簡歷處理用時
100%
簡歷及時處理率
滬公網(wǎng)安備31011502017136號