工作地點：上海 浦東新區(qū) 秋月路26號

What you'll be doing
·         You'll be responsible for DFT verification environment setup, own verification and bringup tasks for Clocks, Boundary Scan, Analog and MBIST, etc. You'll have chance to take the lead role for all ATE verifications and bringup.
·         In long term, you can be DFT lead for verification or extend the expertise to DFT design or implementation.
 
What we need to see
·         BSEE with 3+, MSEE with 2+ years of experience or PhD in DFT or design verification
·         Good understanding on ASIC design and verification
·         Hands on experience on at least one DFT feature: Boundary Scan, 1500, MBIST, Scan, ATPG
·         Experience in silicon debug and bring-up on the ATE is a plus
·         Good exposure to clock design, timing/STA, place-n-route or power is a plus
·         Excellent analytical skills in verification and debug
·         Strong programming and scripting skills in Perl, Python or Tcl desired
·         Excellent written and oral communication skills in English with the curiosity to work on challenges