崗位職責(zé)：
1、負(fù)責(zé)開發(fā)并維護(hù)公司相關(guān)工藝的設(shè)計(jì)支持技術(shù)文件，如設(shè)計(jì)規(guī)則檢查(DRC)文件和開發(fā)并維護(hù)公司相關(guān)工藝的設(shè)計(jì)支持技術(shù)文件，如設(shè)計(jì)規(guī)則檢查(DRC)文件和LVS文件等；
To develop and maintain DRC/LVS and other technical files for related process.
2、開發(fā)并維護(hù)公司相關(guān)工藝的標(biāo)準(zhǔn)器件庫(kù)和參數(shù)化器件庫(kù)
To develop and maintain standard device cells and parameterized device cells for related process. 
3、開發(fā)并維護(hù)PDK集成軟件包
To develop and  maintain integrated PDK package for related process.
4、客戶PDK方面的設(shè)計(jì)支持
PDK application support at customer’s request
5、工程師的PDK知識(shí)培訓(xùn)
Engineer’s PDK knowledge training
6、其他：完成部門經(jīng)理（上級(jí)主管）交辦的其他任務(wù)。
Other: complete the tasks assigned by department manager.

崗位要求：
1、電子工程，半導(dǎo)體物理，微電子等專業(yè)大學(xué)本科畢業(yè)以上。
Bachelor degree, or above, in EE，semiconductor physics, microelectronics etc.
2、具備較扎實(shí)的半導(dǎo)體物理、器件和相關(guān)的集成電路制造工藝知識(shí)，并熟悉代工廠的集成電路設(shè)計(jì)支持流程
Solid knowledge in semiconductor physics, device physics and IC processes, familiar with foundry’s IC design support flow. 
3、在集成電路設(shè)計(jì)公司或代工企業(yè)有3年以上獨(dú)立從事DRC/LVS/版圖設(shè)計(jì)/PDK集成等文件編寫和驗(yàn)證方面的工作經(jīng)驗(yàn)，或有相關(guān)經(jīng)驗(yàn)的優(yōu)秀應(yīng)屆本科畢業(yè)生/研究生；
Above 3 year working experiences with DRC/LVS/layout/PDK-integration in IC design house or foundry(BS/MS graduate well experienced in related IC design support package is also acceptable).
4、熟練使用EXPERT和CADENCE-LAYOUT等集成電路版圖設(shè)計(jì)工具，熟練使用DRACULA/CALIBRE/PAS等相關(guān)工具。
Well experienced in EXPERT and CADENCE EDA layout tools and experienced in DRACULA/CALIBRE/PAS tools.
5、熟悉UNIX操作系統(tǒng)
Very familiar with UNIX
6、流利的英語說、寫、讀流利。
Proficient English in speaking, writing, listening.