- 19萬-30萬/年
- 南京
- |
- 1-3年
- |
- 本科
- |
- 全職
職位誘惑: 技術(shù)領(lǐng)先,成長空間大,年終獎金,五險一金,年度旅游
發(fā)布時間: 2018-08-13發(fā)布
職位描述
1. The candidates should have BS or MS in Electrical Engineering or related.
2. The candidates should have 1~5 years of experience in front-end ASIC design, mainly in Verilog RTL coding, linting and assertion based formal verification.
3. Experience with TCAM/Networking/Storage is a plus.
4. Experience with synthesis and STA is a plus.
5. FPGA emulation experience a plus.
6. Good communication and problem solving skills.
職位發(fā)布者
芯啟源（南京）半導體科技有限公司
HR
7天
簡歷處理用時
100%
滬公網(wǎng)安備31011502017136號