職位描述：
1. Deliver verification plans for different levels; Engage with whole team to understand the project system requirements/Cross block functions.
2. Understand and participate verification environment development; Finish tasks for top/block functional/performance verification.
3. Solid analog background for modeling different blocks, good sense of analog/digital interfaces, to achieve better priority, speed/performance trade off.
4. Develop reusable DV stimulus/checkers/flows. Work closely with team for good mixed signal verification quality and efficiency.

技能要求：
1. BSEE with 3+ years’ /MSEE of industry experience in functional verification and IC design with exposure to all stages of the verification flow.
2. Analog background is a must: such like Bandgap/LDO/OSC knowledge, ADC/DAC/PLL/DCDC will be a plus.
3. Enjoy writing code. Experience in VerilogA/VerilogAMS/System Verilog is preferred.
4. Real number modeling/Behavior modeling experience is a plus.
5. Complex analog- dominant SOC project experience is a plus.
6. Knowledge of VMM/UVM/WREAL, assertions, functional coverage, and formal verification is a plus.
7. Good English communication (spoken and written) ability.