職位描述
1. IP Verification including developing testbench, writing test plan & test case, regressions, coverage and infrastructure development.
2. Apply necessary verification methodologies such as UVM, power aware simulation, formal, etc to achieve the verification goals.

技能描述
1. MSEE from 5 to 15 years DV experience for Staff/Leader/Manager title.
2. Good knowledge of Verilog/SystemVerilog/UVM or VMM and work in Linux platforms.
3. Be skillful in perl/ruby script programming is better.
4. A solid foundation of Computer Architecture and Operating system
5. Have complex ASIC/SOC Design Verification, direct experience in SOC or Processor (GPU or CPU) or Industry bus standard (any of PCI-e, AXI, AMBA) .
6. Good communicate in oral and documentation.
7. Good English hearing, speaking, reading and writing capabilities.
8. Good at learning new technology by self. Has strong interesting on technical.