JOB DESCRIPTION

Processor silicon DDR interface electrical test and debug engineer.  In this role, this senior level engineer will be part of a highly technical team that develops test plans, executes bring-up & test plans, & debugs electrical issues in the memory sub-system of new processors. The job entails extensive hands-on lab work as well as technical leadership and communication across teams.
 
DESCRIPTION OF DUTIES

1) Provides DDR technical leadership in the development of new test & validation features
 
2) Closely interacts with silicon design (DRAM controller and phy) in test execution & debug, as well as in feature definition for future product generation
3) Writes comprehensive electrical & functional test plans for the memory validation of processors
 
4) Executes electrical & functional test plans for AMD processors using hardware & software validation tools, oscilloscopes, & logic analyzers.

5) Debug of electrical & functional issues of the memory sub-system of new processors
 
6) Provides detailed input into the platform definition & review of platform designs used in the silicon validation of new processors.

7) Provides technical guidance and training to less experienced engineers and technicians in the planning, test, & debug of the memory sub-system.
SKILLS REQUIRED

1) BS-EE / BS-CE with at least 5 years directly related experience. An advanced degree will be considered a plus.

2) Requires experience and demonstrated technical expertise in the development & execution of platform level electrical & functional test plans. DDR3/4 Memory test experience on electronic components such as uProcessors would be considered a big plus.  

3) Requires extensive hands-on experience and demonstrated technical expertise in the debug of I/O interfaces such as DDR

4) Demonstrated experience with or knowledge using oscilloscopes, reading schematics and layout documentation
5) Requires good written and oral communication skills.  
6) Demonstrated ability to communicate with a variety of engineering disciplines and management.