Role & Responsibilities:
Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place & route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery.
 
Job Requirements:
-      MSEE or Bachelor with 3 – 20 of industrial experience in ASIC physical design
-      Experience in physical design of deep submicron digital ASIC chips
-      Hands on experience in large scale ASIC chip physical design
-      Knowledgeable in all aspects of deep submicron ASIC design flow
-      Successfully gone through several complete product development cycles
-      Demonstrate strong leadership and work well with cross-functional teams
-      Good listening, writing and speaking English
-      Good communication skills, strong interpersonal skills and the flexibility
-      Dedicated, hardworking and good team player
-      Familiar with Back-End (physical design) EDA tools
-      Familiar with Front-End EDA tools is a plus
-      Familiar with Unix/Linux environment and good at scripts