Job Description:
This position is IP developer. The candidate will be expected to develop and verify Basic Core Modules for Synopsys IP interface products. The responsibilities include, but not limited to, RTL implementation and verification for IPs to be used for ASIC flow, improving testability and test coverage of the IP components, etc. the position is located in Shanghai, but need work closely with worldwide IP development team.
  
  Requirements:
- 3 to 5years relevant experience in ASIC/FPGA design of communications or consumer applications.
- Must have strong knowledge on RTL coding with Verilog/VHDL/SystemVerilog
- Must have good understanding on RTL verification methodology
- Experience in data-path logic design, clock domain crossing design, synthesis, simulation, formal verification
- Knowledge of one or more following areas is a big plus
- Experience in computer arithmetic (floating point, fixed point, and integer operations), static timing analysis
- Experience in Digital Signal Processing design, low power data-path design
- Familiar with EDA tools, like DC, VCS, Formality, Spyglass, DFT compiler, Synplify, etc.
- Familiar with shell/Perl/Tcl scripting
- Strong written and verbal communication skills
- Self-motivated, quick learner, and a good team player