- 30萬-50萬/年
- 成都
- |
- 3年以上
- |
- 碩士
- |
- 全職
職位誘惑: 五險一金,福利好,技術(shù)領(lǐng)先,成長空間大,通訊津貼,交通補助,節(jié)日禮物,技能培訓(xùn)
發(fā)布時間: 2019-02-27發(fā)布
職位描述
JOB DESCRIPTION:
- Engaged in SOC/ASIC module-level and system verification
- Individually develop test plan and set up UVM verification environment
- Create constrained random and C pattern testcase
- Engaged in Gate-level simulation with SDF annotation and Low-power with UPF
- Participate in digital/analog mix-signal Co-simulation
- Develop/maintain/enhance environment/scripts/makefiles
QUALIFICATION:
- BSEE with minimum 3-year experience in SOC/MCU verification
- Proficiency in Systemverilog/ Verilog/C
- Solid knowledge on advanced verification methodology,UVM is preferred
- Good knowledge on ARM architecture,AMBA2.0 and AMBA3.0
- Experience on scripting language,Perl and shell are preferred
- Hands on experience with simulation and verification tools, such as VCS/NC
- Experience on DDR/USB/Serdes is plus
- Familiar with FPGA flow is preferred
- Strong teamwork and communication ability
職位發(fā)布者
滬公網(wǎng)安備31011502017136號