- 25萬-50萬/年
- 上海
- |
- 3年以上
- |
- 本科
- |
- 全職
職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,福利好,免費(fèi)班車,交通補(bǔ)助,技術(shù)領(lǐng)先,成長空間大
發(fā)布時(shí)間: 2022-03-21發(fā)布
職位描述
Job Responsibilities:
- Responsible for Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
- Responsible for ASIC design methodology and flow development, interfacing with EDA vendors on technology.
Job Requirements:
- MS degree of EE.
- Familiar with Verilog RTL design and has experience of large digital ASIC project.
- Familiar with front-end EDA tools and flows (Design compiler, PrimeTime, Conformal,Verde)
- Familiar with unix/linux and scripts (tcl, perl etc.)
- Fluent English on talking, presentation and writing documents.
- Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
職位發(fā)布者
vicky cai
HR
7天
簡歷處理用時(shí)
100%
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