Job Description
·        Understanding DFT feature requirements & DPPM goals & coming up with appropriate DFT specifications for the ASIC
·        Implementing DFT like Scan, MBIST, TAP, LBIST, IO & SerDes DFT etc
·        Working closely with STA Engineers on test signoff timing
·        Generating, Verifying & Debugging Test vectors before tape release using Verilog simulators like VCS
·        Validating & Debugging Test vectors on ATE during silicon bring up phase
·        Support Synthesis and STA task
·        Helping with silicon failure analysis, diagnostics & yield improvement efforts
·        Be a highly-valued member of our start-up like team through excellent collaboration and teamwork with other teams
·        Innovating newer DFT solutions to solve testability problems in 40nm, 28nm & beyond
·        Automating DFT & Test Vector Generation flows
Qualifications
·         BS degree or higher in EE, CE, or CS
·         2+ years hands-on experience as DFT/Synthesis/STA engineers
·         Good knowledge on DFT (such as IO and Analog DFT, ATPG and/or Scan, BIST, and others)
·         Good knowledge on ASIC design flow and tools (including simulation, synthesis, formal check and STA)
·         Scan Insertion and scan compression background (DFTMAX, TK , Tessent )
·         Strong debugging and analytical skills
·         Familiar with UPF and low power
·         Memory BIST and Logic BIST design and debug experience (MBISTArchitect)
·         Well-versed in ATPG vector generation, simulation, debug. (TetraMax, Fastscan, Tessent )
·         Experience in Verilog coding, testbench generation & simulation
·         Experience working on ATE is a plus
·         English documents reading
·         Good programming in Perl/Python, TCL and Shell programming
·         Self-motivated, team work, and good communication skills