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ASIC Design Engineer 數(shù)字芯片設(shè)計(jì)工程師

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  • 25萬(wàn)-50萬(wàn)/年
  • 上海
  • |
  • 工作經(jīng)驗(yàn)不限
  • |
  • 本科
  • |
  • 全職

職位誘惑: 股票期權(quán),年終獎(jiǎng)金,五險(xiǎn)一金,福利好,老板nice,技術(shù)領(lǐng)先,成長(zhǎng)空間大,節(jié)日禮物

發(fā)布時(shí)間: 2019-05-17發(fā)布

職位描述


·        Independent block and SoC RTL design and verification
·        Analog and digital IP integration
·        RTL handoff quality check using EDA tools
·        Prepare signoff quality full chip SDC file
·        Prepare signoff quality full chip UPF file
·        Support ASIC implementation
·        Support FPGA prototyping
·        Support DFT integration
·        Support software and system production
·        Write design documents
Qualifications
·        2+ years hands-on experience in ASIC RTL design. Experience in Bluetooth, Mobile Computing or IoT is a plus
·        Familiar with popular ASIC solutions (including specification and architecture)
·        Familiar with ASIC design verification and implementation flow
·        Familiar with relevant QA tools (for example Spyglass)
·        Strong debugging and analytical skills, generate ideas, and provide innovative solutions to solve technical problems
·        English documents reading
·        Good programming in Perl/Python, TCL and Shell programming
·        Self-motivated, team work, and good communication skills


 

職位發(fā)布者

魯冬梅

HR

7天

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