- 15萬-25萬/年
- 上海
- |
- 1-3年
- |
- 本科
- |
- 全職
職位誘惑: 五險一金,福利好,老板nice,技術(shù)領(lǐng)先,成長空間大,技能培訓(xùn)
發(fā)布時間: 2019-06-28發(fā)布
職位描述
Description
- As a team member to design and verification next-generation Mixed-Signal Communication SoC
- Digital IC design from RTL to netlist including synthesis, timing constraint composing, DFT, ECO
- Digital IC design including synthesis, verification, algorithm implementation, etc.
- Program development in TCL/Python/... to improve productivity
- BS/MS in ME, EE or CS.
- Positive, active, self-motivated and teamwork
- 2+ years of hands-on experience in IC design industry
- Experiences on Cadence, Synopsys, Mentor EDA tools
- Real tape-out experience is a good plus
- Familiar with UVM verification methodology is a plus
- Experiences on verification on FPGA and familiar with FPGA EDA tools is a plus
- Familiar with HW/SW interface, any CPU ISA like RISC-V/ARM/MIPS/... is a plus
- Network/Communication System/DSP/Mixed-Signal/Automotive design experience is a plus
職位發(fā)布者
郭雄飛
設(shè)計總監(jiān)
7天
簡歷處理用時
100%
簡歷及時處理率
滬公網(wǎng)安備31011502017136號