崗位描述
1、基于PAS平臺(tái)/skill語言獨(dú)立開發(fā)PDK library，包括pcell,callback,CDF,symbol view等。
To develop PDK library based on PAS/skill language independently, including pcell,callback,CDF,symbol view.
2、熟練使用Cadence virtuoso，calibre等相關(guān)EDA工具，獨(dú)立完成PDK的仿真驗(yàn)證及物理驗(yàn)證
Well experienced in Cadence virtuoso，calibre relevant EDA tools, complete physical verification and simulation verification independently.
3、熟悉器件物理結(jié)構(gòu)、Layout Design Rule及spice model，能根據(jù)客戶及工藝的具體要求完成PDK的開發(fā)
 Familiar with device physical structure, Layout Design Rule and spice model, to develop PDK based on customerand process requirement.
4、學(xué)習(xí)TCL/perl等腳本語言，實(shí)現(xiàn)PDK開發(fā)和驗(yàn)證的自動(dòng)化
 To study TCL/perl script, realize PDK development and verification automatization 
5、客戶PDK-Pcell方面的設(shè)計(jì)支持
PDK application support at customer’s request
6、工程師的PDK知識(shí)培訓(xùn)
Engineer’s PDK knowledge training
7、其他：完成部門經(jīng)理（上級(jí)主管）交辦的其他任務(wù)。
Other: complete the tasks assigned by department manager.

所需教育水平與技能 (EDUCATION AND EXPERTISE REQUIRED)
1、電子工程，半導(dǎo)體物理，微電子等專業(yè)大學(xué)本科畢業(yè)以上。
Bachelor degree, or above, in EE，semiconductor physics, microelectronics etc.
2、具備較扎實(shí)的半導(dǎo)體物理、器件和相關(guān)的集成電路制造工藝知識(shí)，并熟悉代工廠的集成電路設(shè)計(jì)支持流程
Solid knowledge in semiconductor physics, device physics and IC processes, familiar with foundry’s IC design support flow. 
3、在集成電路設(shè)計(jì)公司或代工企業(yè)有3年以上獨(dú)立從事DRC/LVS/版圖設(shè)計(jì)/PDK集成等文件編寫和驗(yàn)證方面的工作經(jīng)驗(yàn)，或有相關(guān)經(jīng)驗(yàn)的優(yōu)秀應(yīng)屆本科畢業(yè)生/研究生；
Above 3 year working experiences with DRC/LVS/layout/PDK-integration in IC design house or foundry(BS/MS graduate well experienced in related IC design support package is also acceptable).
4、熟練使用EXPERT和CADENCE-LAYOUT等集成電路版圖設(shè)計(jì)工具，熟練使用DRACULA/CALIBRE/PAS等相關(guān)工具。
Well experienced in EXPERT and CADENCE EDA layout tools and experienced in DRACULA/CALIBRE/PAS tools.
5、熟悉UNIX操作系統(tǒng)
Very familiar with UNIX
6、流利的英語說、寫、讀流利。
Proficient English in speaking, writing, listening.