崗位描述
1、熟悉半導(dǎo)體工藝流程、器件物理結(jié)構(gòu)
  Familiar with semiconductor process flow, device physical structure
2、掌握calibre/ICV/PVS物理驗(yàn)證工具，并能夠獨(dú)立開發(fā)DRC/LVS
  Proficient at calibre/ICV/PVS physical verification tools, to develop DRC/LVS independently
3、掌握StarRC/QRC/xRC寄生參數(shù)抽取工具，并能夠獨(dú)立開發(fā)LPE
Proficient at StarRC/QRC/xRC parasitic parameter extract, to develop LPE independently
4、掌握Virtuoso版圖設(shè)計(jì)工具，能夠獨(dú)立完成DRC/LVS/LPE的驗(yàn)證
Proficient at Virtuoso, complete DRC/LVS/LPE verification independently
5、學(xué)習(xí)TCL/perl等腳本語言，實(shí)現(xiàn)開發(fā)與驗(yàn)證自動(dòng)化
To study TCL/perl script, realize Runset development and verification automatization 
6、客戶PDK-Runset方面的設(shè)計(jì)支持
PDK application support at customer’s request
7、工程師的PDK知識培訓(xùn)
Engineer’s PDK knowledge training
8、其他：完成部門經(jīng)理（上級主管）交辦的其他任務(wù)。
Other: complete the tasks assigned by department manager.

所需教育水平與技能 (EDUCATION AND EXPERTISE REQUIRED)
1、電子工程，半導(dǎo)體物理，微電子等專業(yè)大學(xué)本科畢業(yè)以上。
Bachelor degree, or above, in EE，semiconductor physics, microelectronics etc.
2、具備較扎實(shí)的半導(dǎo)體物理、器件和相關(guān)的集成電路制造工藝知識，并熟悉代工廠的集成電路設(shè)計(jì)支持流程
Solid knowledge in semiconductor physics, device physics and IC processes, familiar with foundry’s IC design support flow. 
3、在集成電路設(shè)計(jì)公司或代工企業(yè)有3年以上獨(dú)立從事DRC/LVS/版圖設(shè)計(jì)/PDK集成等文件編寫和驗(yàn)證方面的工作經(jīng)驗(yàn)，或有相關(guān)經(jīng)驗(yàn)的優(yōu)秀應(yīng)屆本科畢業(yè)生/研究生；
Above 3 year working experiences with DRC/LVS/layout/PDK-integration in IC design house or foundry(BS/MS graduate well experienced in related IC design support package is also acceptable).
4、熟練使用EXPERT和CADENCE-LAYOUT等集成電路版圖設(shè)計(jì)工具，熟練使用DRACULA/CALIBRE/PAS等相關(guān)工具。
Well experienced in EXPERT and CADENCE EDA layout tools and experienced in DRACULA/CALIBRE/PAS tools.
5、熟悉UNIX操作系統(tǒng)
Very familiar with UNIX
6、流利的英語說、寫、讀流利。
Proficient English in speaking, writing, listening.