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Cadence

Lead Application Engineer (數(shù)字后端)

收藏職位
  • 我要分享
  • 30萬(wàn)-45萬(wàn)/年
  • 深圳
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全職

職位誘惑: 老板nice,股票期權(quán),成長(zhǎng)空間大,技術(shù)領(lǐng)先

發(fā)布時(shí)間: 2021-01-12發(fā)布

職位描述

Position Description:
1. To provide key technical support in digital IC design implementation, product demonstration, and sales presentations.
2. To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power and high-performance designs.
3. Have real design experience including floorplan and partition, place, CTS, route, STA timing closure, Physical verification, RC extraction, Power Network analysis.
4. Assist in technical evaluation, assessment and delivery of concurrent ASIC/SoC designs.
5. To play a leading role among other team members, while receive little instruction on routine and general assignments.
 
Position Requirements:
1. A bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications.
2. Ability to understand and articulate technical issues, (and knowledge of) design products and their applications.
3. Requires working knowledge of one or more programming languages, and effective communication and soft skills.
4. An MS degree and/or working experience in multi-nation IC design house/or familiar with EDI/Innovus product is a plus.
5. Good communication in English and good work attitude.
6. Be familiar with shell/Perl/Tcl etc. script language.

職位發(fā)布者

cadence hr

Sr.Manager&BP

7天

簡(jiǎn)歷處理用時(shí)

99%

簡(jiǎn)歷及時(shí)處理率

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