As a junior design/verification engineer in Defender Chip, you will work in a highly innovative and motivated environment. Supported by our customized SPARC Core, we can offer you a unique experience of designing/modification of CPU core on SOCs. In addition, you will be dedicated to security chip/TPM chip development and travel through many elements across information security and SOC designs.

Joining a fabless start up brings great oppotunities as well as challenges ahead. We appreciate those who could grow with us in the long run while providing variety of development paths and oppotunities of stock options.

Job responsibilities:

1. Fully understand design specs.
2. Learn and perform development activities, including RTL design, synthesis, Formal Verification, and Static Timing Analysis
3. Unit-level and System-level verification
4. Chip level integration
5. Provide support to senior engineers, simulate, analyze and debug current chip designs, include emulator and FPGA based HW and FW co-verification testing.

Qualifications:
1. Bachelor or Master's degree major in CS/EE/Math, preferable from a prominent university(985/211) and with good academic results.
2. Verilog RTL coding experience, including in-school projects.
3. Proficiency in English is a must.
4. Excellent analytical and debugging skills, ability to cooperate and working in a team.
5. Experience with design and verification flow preferred.
6. Synthesis, Simulation, Static Timing Analysis experiences preferred.