IC Design Manager/Team Lead/Staff IC designer

Responsibilities:

Lead team and/or work as individual contributor to design and implement the company’s cutting-edge SoCs, includes:

-   SoC partitioning and interface definition

-   Block level design, RTL coding, and verification

-   Specify IP requirements according to product specification, seek and evaluate third party IPs.

-   Design reviews and verification coverage analysis

-   Run Synthesis, formal check, STA; Coordinating backend design, FPGA emulation and silicon bring up

Qualification:

-   MSEE /MSCE with 5+ years(8+ years for manager) experience on IC design, or equivalent

-   Strong skill on Verilog HDL, and matlab/C/C++

-   Multiple projects experience on IC design from specification to netlist.

-   Experience on SoC hardware/software co-design, verification and bring up

-   Well organized, strong communication skill, work smart, and result oriented

-   Experience on one or more of the following is a plus:

a)      Architecture design, partition, and integration of multi-core RISC or DSP

b)      Mapping algorithm to RTL for computer arithmetic or signal processing

c)      Various SoC components, such as on chip bus architecture, level 2 cache/Flash Cache, DDR, USB, QSPI Flash booting, etc 

d)      Hands on experience on low power design, such as multiple Vt, multiple Vdd, dynamic voltage scaling, etc.

IC設(shè)計(jì)經(jīng)理/主管/高級(jí)設(shè)計(jì)工程師

職責(zé)描述：

帶領(lǐng)團(tuán)隊(duì)或作為個(gè)體貢獻(xiàn)者完成公司領(lǐng)先的語(yǔ)音處理SOC芯片設(shè)計(jì)，包括但不限于：

-   SoC 子系統(tǒng)劃分和接口定義

-   模塊級(jí)設(shè)計(jì)，RTL編碼和驗(yàn)證

-   根據(jù)產(chǎn)品規(guī)格細(xì)化IP需求，尋找并評(píng)估第三方IP.

-   定期開(kāi)展Design reviews 和驗(yàn)證覆蓋率分析

-   完成芯片綜合, 等效性分析，時(shí)序分析，協(xié)調(diào)后端 APR設(shè)計(jì),完成時(shí)序收斂， FPGA 驗(yàn)證 和 芯片 bring up

任職資格:

-   碩士畢業(yè)，5年以上(設(shè)計(jì)經(jīng)理需要8年以上) IC 設(shè)計(jì)項(xiàng)目經(jīng)驗(yàn)，或同等經(jīng)歷。

-   熟練掌握和使用Verilog HDL, and matlab/C/C++

-   主導(dǎo)或參與過(guò)多個(gè)從規(guī)格書(shū)到netlist的芯片前端設(shè)計(jì)項(xiàng)目.

-   具有SoC 軟硬件協(xié)同設(shè)計(jì),驗(yàn)證和 bring up的經(jīng)驗(yàn)

-   具備較強(qiáng)的溝通能力和組織協(xié)調(diào)能力，結(jié)果導(dǎo)向

-   具備以下一項(xiàng)或多項(xiàng)經(jīng)驗(yàn)將優(yōu)先考慮:

a)      SOC架構(gòu)設(shè)計(jì), 軟硬件劃分， 多核異構(gòu)SOC設(shè)計(jì)

b)      信號(hào)處理和計(jì)算機(jī)算法的硬件實(shí)現(xiàn)

c)      熟悉常見(jiàn)的SOC組件, 如 片上總線架構(gòu), level 2 cache/Flash Cache, DDR, USB, QSPI Flash booting等 

d)      低功耗設(shè)計(jì)的實(shí)戰(zhàn)經(jīng)驗(yàn), 如 multiple Vt, multiple Vdd, dynamic voltage scaling, 等