數(shù)字驗證工程師 / Digital Verification Engineer
- 40萬-45萬/年
- 上海
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- 3年以上
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- 本科
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- 全職
職位誘惑: 五險一金,福利好,老板nice
發(fā)布時間: 2019-08-28發(fā)布
職位描述
1、負責數(shù)字模塊和系統(tǒng)級驗證;
2、制定高覆蓋率驗證計劃和搭建驗證環(huán)境;
3、生成隨機化測試向量;
4、執(zhí)行帶有時序參數(shù)門級仿真驗證;
5、協(xié)助FPGA工程師搭建并調(diào)試FPGA驗證環(huán)境。
1, Responsible for digital module level, and system level verification.
2, Make verification plan with high coverage and build verification environment.
3, Generate random test vector.
4, Simulate gate-level netlist with timing parameters.
5, Support the FPGA engineer to build and debug the FPGA verification environment.
崗位要求:
1、電子工程類本科及以上學歷,三年及以上經(jīng)驗;
2、熟悉數(shù)字電路驗證流程;
3、精通Systemverilog/Verilog/C語言;
4、精通覆蓋率模型、帶約束的隨機向量生成等驗證方法學(UVM);
5、熟練運用tcl/perl/makefiles等腳本;
6、熟練掌握Cadence邏輯仿真工具;
7、具有數(shù)?;旌戏抡娼?jīng)驗者尤佳;
8、具有CMOS圖像傳感器芯片驗證經(jīng)驗尤佳;
9、具有較強的學習能力,獨立解決問題能力和良好的團隊合作精神。
1, Electrical engineering bachelor degree or above, 3 years or above experience;
2, Familiar with digital verification flow.
3, Proficient in Systemverilog/Verilog/C.
4, Proficient in coverage model, random constrained vector generated verification methodology (UVM).
5, Have ability of writing TCL/perl/makefiles script.
6, Familiar with Cadence logic simulation tools.
7, Having experience in mix signal simulation is preferred.
8, With CIS chip verification experience is preferred.
9, Have strong ability of learning, problem solving and good team work spirit.