崗位職責(zé):
This is a challenging job role to build/enhance top/block PNR flow in advanced technology node(7nm and beyond)
o Drive best methodology/flow implementation and work at real design in one or multiple of the following areas:
o Methodology/flow infrastructure (e.g. flow tracer, etc.).
o Synthesis/DFT.
o Top level floorplan/PG-plan, feedthrough, pin assignment. repeater/pipeline insertion, chip assembly, bump PNR.
o Full chip/block STA/RC extraction.
o Physical Verification.
o Block level PNR, CTS,H-Tree building.
o Power/IR/EM analysis
o Clock Mesh construction and simulation/annotation.
o Timing/SI, IR/EM/self heat signoff.

任職資格:
o PhD or MSc in the areas of Electrical Engineer, Computer Science with great logical thinking skill and memorization.
o Strong communication skill in both English and Chinese is a multi-site team environment is a must.
o Strong EE fundamentals (analog/digital circuit design, signal and power integrity). Hands-on experience with debug of EDA tool and flow is a must.
o Strong programming skills in Perl/Python/Tcl.
o Proficiency in simulation tools and experience with data analysis and interpretation a plus.
o Proficiency in device/technology, VLSI design, Synthesis/DFT, timing signoff, STA and STA tool behavior, RC extraction, top/block physical design, ASIC CAD/Methodology.
o Experience with server CPU/GPU, design, integration and flow development is desired
o Exposure to structured software development a plus (data management, unit testing, code reviews)
o Familiar with and deep understanding of the behavior of PrimeTime, ICC2, starRCXT, redhawk, power theatre, etc is a plus