ASIC Design Engineer
- 32萬-48萬/年
- 北京
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- 5年以上
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- 本科
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- 全職
職位誘惑: 年終獎金,五險一金,福利好,老板nice,技能培訓(xùn),成長空間大,技術(shù)領(lǐng)先
發(fā)布時間: 2022-11-10發(fā)布
職位描述
崗位職責(zé):1. SOC front-end design, including clock, reset, system control, top interface2. Responsible for RTL quality and module level synthesis3. Support DV for function verification4. Support software driver development
任職資格:1. minimum 3+/6+ years of ASIC design, 2. Proficient in Verilog HDL, knowledge of system architecture and design3. Solid working experience with Arm architecture and AMBA 4. Familiar with front-end design flow and EDA tools5. Strong problem solving, communication skills and good team work spirit6. solid knowledge in one of the following area: ? DDR/HBM Memory controller? PCIE design? GFX design