Job Responsibilities:
·       Develop micro-architecture for USB blocks based on architectural requirement.
·       Develop RTL code for USB blocks in Verilog HDL and make sure functional correct and reusable for different configuration.
·       Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floor planning and close timing.

• Analyze gating efficiency report to improve RTL quality.

Job Requirements:
·       MS degree of EE with 10+ years working experience in ASIC Company.
·       Expert of Verilog RTL design and has experience of large digital ASIC project.
·       Familiar with front-end EDA tools and flows.
·       Familiar with Unix/Linux and scripts (tcl, perl, ruby and etc.)
·       Fluent English on talking, presentation and writing documents.
·       Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager.
·       Can solves complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation.
·       Possesses specialized knowledge of computer architecture and computer arithmetic.
·       Possesses specialized knowledge of PCIE and AMBA.
·       Possesses specialized knowledge of USB and Thunderbolt (a plus)..