Responsibility:
The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include technical leading on the following tasks from time to time: specification, top level SOC design tasks, HDL coding, etc.
 
Requirements:
The candidate is preferred to be MSEE with minimum of 6 years, or BSEE with minimum of 8 year experiences in digital ASIC/SOC design engineering.  
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge that facilitates integrative thinking, , driving execution of quality and timely result, capability  to solve complex, novel and no-recurring problems and decision-making on critical technical areas