- 26萬-50萬/年
- 上海
- |
- 5年以上
- |
- 本科
- |
- 全職
職位誘惑: 年終獎(jiǎng)金,股票期權(quán),天天下午茶,年度旅游,交通補(bǔ)助,技能培訓(xùn)
發(fā)布時(shí)間: 2020-02-11發(fā)布
職位描述
Responsibilities
1. Implement DFT structures (internal-scan (stuck-at, at-speed), JTAG, MBIST, hard IP testing structure) in complex SOC design；
2. Generating, simulation and debugging the test patterns for ATE manufacture testing；
3. Interface with back-end physical design team to complete timing closure for test related logic；
4. Interface with operation team to debug production test-vectors for wafer test and final test.
Requirements:
1. BS or MS, major in EE or related discipline;
2. 5+ years work experience in SOC DFT design;
3. Strong experience in ASIC logic design and verification;
4. Logical thinking and sensitive to the problem with good self-study and problem shooting ability;
5. Good communication capability and teamwork spirit.
更多地平線愿景可戳Bloomberg Markets: China Open 采訪：https://mp.weixin.qq.com/s/4DtSP1rfqByShkuPQ0o_-g
職位發(fā)布者
李莉萍
HR
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