Job Description:
Focus on analog/digital mixed IP and Chip design&implementation. The engineers need to act as a strong team member and contributor, who also need to collaborate with analog team and backend team. 
Responsibilities:
1.Define IP block spec and micro-architecture.
2. Be in charge of RTL-coding, simulation, synthesis and related F.E flow, support B.E to closure, and support silicon debugging.
3. Be in charge of subsys or chip integration and implementation.
4. Analyze and Optimize for PPA.
Requirements:
1. BS with 4+ years, MS with 3+ years of experience in ASIC or FPGA design.
2. Good skill in the field of digital logic design, whole digital design flow, especially lint/cdc/synthesis/sta/formal check.
3. Good knowledge of some general high speed interface IPs is preferred : USB, PCIE, MIPI, etc.
4. Scripting and automation skill (tcl, perl, makefile, python etc) is a plus.
5. Individual contributor in 3+ design projects with successful completion.
6. Self motivated, good communication skill and team work spirit.
7. Fluent in both English and Chinese.