Bluetooth Design/Verification Engineer 藍(lán)牙芯片設(shè)計(jì)驗(yàn)證工程師（實(shí)習(xí)生）

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6萬-12萬/年
上海
|
應(yīng)屆生/在校生
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碩士
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實(shí)習(xí)

職位誘惑: 年終獎(jiǎng)金,五險(xiǎn)一金,福利好,老板nice,股票期權(quán),技能培訓(xùn),節(jié)日禮物,成長(zhǎng)空間大,技術(shù)領(lǐng)先,年度旅游

發(fā)布時(shí)間: 2019-05-17發(fā)布

職位描述

Job Description
·        Bluetooth baseband and modem integration for SoC and verification
·        RTL handoff quality check using EDA tools
·        Prepare relevant SDC file
·        Prepare relevant UPF file
·        Co-work and Support ASIC implementation
·        Co-work and Support FPGA prototyping
·        Co-work and Support software and system productions
·        Write design documents
Qualifications
·        2+ years hands-on experience in RTL design, integration, verification in Bluetooth & BLE Baseband and Modem.
·        ASIC design verification and implementation knowledge
·        Good knowledge to RTL QA tools (for example Spyglass)
·        Good knowledge to UPF and low power verification (for example VCLP and VCS-NLP)
·        Good knowledge to Matlab
·        English documents reading
·        Good programming in Perl/Python, TCL and Shell programming
·        Good team work and communication skills