JOB DESCRIPTION: 
- Write Micro-Architecture Definition/Writing Design Implementation Spec；
- Write RTL coding for block or top level；
- Do IP level synthesis / timing analysis / formality check / CDC check /Code coverage check；
- Assist on Verification Engineer to complete module and top level simulation and verification;
- Debug RTL/Gate Level waveform at module or top level;
- Do Silicon debugging of the related module functionalities and provide ECO solution accordingly；
 
QUALIFICATION: 
- MSEE with 4+ year experience of digital design;
- Relevant experience in high speed IO IP design, and PCIe design experience is a big plus;
- Very Strong skills of Verilog RTL coding, simulation debug and base or metal layer ECO;
- Hands on experience in EDA tools such as Cadence NC-Sim, Synopsys DC, PT, etc;
- Strong skills of Script and be familiar with TCL, Perl, etc.
- Self-motivated, good team work spirit and good communication skills;