Job Overview             
We are seeking CPU microarchitecture engineers to develop the next generation of high performance RISC-V CPUs. Individuals in this team will be involved in all phases of product development, from proving-out initial high-level concepts down to modeling the bits of individual registers. We need engineers who can help us design and implement CPU microarchitecture. In this team, individuals will work with CPU performance modeling team and verification team to design the major blocks of the next generation custom RISC-V CPU. Use Hardware Description Language to design models of the Instruction Unit, Execution Unit, Storage Unit, Caches and coherence bus system. Employ synthesis, STA and power tools to achieve improve performance with reasonable overhead.
 
Location:
Beijing/Shanghai
 
Minimum Qualifications
We are looking for individuals that have 3+ years’ experience or equivalent education in the following areas:
 
1.     Good understanding of RISC and CPU architecture
2.     High performance logic design techniques
3.     Familiar with Verilog/VHDL, and behavior modeling
4.     Experience with simulation and design flow, such as lint, CDC, synthesis, STA, floorplan and etc.
 
Preferred Qualifications          
 
Additional skills in the following areas are a plus:
1.     Industry experience in a specific high performance CPU design.
2.     Experience with CPU function unit, such as instruction unit, execution unit and O3 related logic.
3.     Experience with CPU memory system unit, such as Load/Storage unit, TLB, MMU.
4.     Experience with coherence protocol implementation, such as ACE, CHI. 
5.     Knowledge of verification and good communication skill with verification team
 
Education Requirements         
Required:  Master’s, Electronic Engineering and/or Computer Science
Preferred: Doctorate, Electronic Engineering and/or Computer Science or equivalent experience.