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Synopsys

Emulation Application Engineer ( ZeBu)

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  • 我要分享
  • 40萬-50萬/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全職

職位誘惑: 年終獎金,五險一金,技術(shù)領(lǐng)先,成長空間大,技能培訓(xùn)

發(fā)布時間: 2021-09-13發(fā)布

職位描述

Job Title: Emulation Application Engineer ( ZeBu)
Location: Shanghai

Description:
Verification is the number one bottleneck in SOC designs today. Synopsys is uniquely positioned to offer the most complete verification solution in market today.
ZeBu is the emulation platform for Synopsys verification flow, it’s the industry’s performance & capacity leader in Emulation. VCS is the simulation platform for Synopsys verification flow, it incorporates a suite of built-in high performance next generation technologies for test bench automation, assertion based verification, coverage closure, etc., which are needed for verifying challenging multi-million gate designs.
As a Senior AE for Verification, based in Shanghai, candidate will be responsible for successful deployment of Synopsys verification flow to a growing customer base in Asia Pacific.
The AE responsibilities include onsite deployment of industry leading automation and verification technologies, creation of technical collateral, defining new methodology, and product support, testing and writing specifications for enhancement.
Candidate will be responsible to interact with and support customers, sales, and marketing, and help analyze and resolve  complex verification issues for customers cutting edge ASIC designs.
The position offers a great opportunity to grow by learning state-of-art verification flows from Synopsys.
Requirements: 

  • MS or PhD majored in EE with more than 5 years of IC design/verification/emulation experiences.
  • Good knowledge of high-level design methodologies and strong communication skills are required.
  • Ability to work with customers and R&D teams is important. Real project experience in ASIC/SoC emulation and good expertise on popular emulators like Palladium/Veloce/Zebu are required.
  • Proficient with HDL (Verilog/VHDL), HVL(e/vera/system Verilog), C/C++, Unix, and having a strong understanding of ASIC design flows, VLSI, and/or CAD-engineering.
  • Experience on VMM/OVM/UVM and knowledge of simulator-emulator co-emulation are preferred.

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7天

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