Analog Design Verification Engineer
- 20萬-30萬/年
- 北京
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- 應(yīng)屆生/在校生
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- 碩士
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- 全職
職位誘惑: 技術(shù)領(lǐng)先,成長空間大,技能培訓(xùn),福利好,年終獎金
發(fā)布時間: 2019-09-26發(fā)布
職位描述
Responsibilities:
- Be expected to contribute to analog circuit design, simulation, directing layout and silicon debugging.
- Design analog products and blocks such as ADC/DAC, operational amplifier, comparator, voltage reference, oscillator, error amplifier, voltage regulator etc.
- Participate in mix-signal IC product development, working with multi-site engineers on different functions.
- Work with application and test engineers to define optimal characterization and test solution.
- Responsible for mixed-signal functionality verification architecture and testbench design by using advanced verification methodologies.
Requirement:
- MSEE or above in EE, PHD is a strong plus
- Transistor-level circuit design, simulation, and layout of analog /mixed-signal integrated circuit, with track record of high-quality circuit design.
- Solid understanding of device physics, control theory and sampling system is a strong plus.
- Prior experience with ADC related IC designs a strong plus.
- Matlab/Simulink/VerilogA or other behavioral simulation expertise a plus.
- Innovative, with ability to raise good questions.
- Self-motivation, result oriented, good team work and communication skills.
- Good spoken and written English