Your responsibilities will include:
DfT architecture definition for digital/mixed signal IPs
DfT logic/circuit implementation for SoC
DfT pattern generation, simulations and debug (including setup creations, any required automation, etc.)
overcome the different design and IP challenges to enable achieving all the structural coverage goals
Drive new techniques and methodologies to enable test timeand test cost reduction for the SoCs
SoC DfT verification in RTL and Gate Level
Responsible for driving the requirements with all the stakeholders

Minimum requirements:
more than 3 years of relevant experience
A understanding of mixed signal chip/IP level DfT
Design experience in MBIST is an added advantage
Exposure to post silicon debug is a plus
Excellent debugging and problem solving skills
Effective communication skills to interact with all stakeholders
Ability to solve problems using a systematic approach

Preferred qualifications:
• Demonstrated strong analytical and problem solving skills
• Strong verbal and written communication skills
• Ability to work in teams and collaborate effectively with people in different functions
• Strong time management skills that enable on-time project delivery
• Demonstrated ability to build strong, influential relationships
• Ability to work effectively in a fast-paced and rapidly changing environment
• Ability to take the initiative and drive for results